Tsmc Standard Cell Naming Convention May 2026

| Field | Example codes | |--------------|----------------------------------------| | Function | INV, NAND2, DFFR, AOI21 | | Drive | X0.5, X1, X2, X4, X8, X16 | | Vt | LVT, RVT, HVT, ULVT, ELVT | | Physical | _D, _P, _F, _CK, _ISO, _LS | | Track height | 6T, 7.5T, 9T (node dependent) |

| Code | Track height (metal 2 pitch) | |--------|------------------------------| | 6T | 6 tracks | | 7.5T | 7.5 tracks | | 9T | 9 tracks (high performance) | tsmc standard cell naming convention

| Code | Meaning | |-----------|--------------------------------------------------------| | (none) | Regular height, standard pin placement | | _D | Double-height cell (for higher drive or reduced IR drop) | | _P | Pin access optimization (better routing) | | _F | Flip-pin (mirrored for abutment) | | _CK | Clock-specific cell (low jitter) | | _ISO | Isolation cell (power gating) | | _LS | Level shifter | | _RO | Ring oscillator cell (test) | In N7, N5, N3, TSMC uses multiple metal track heights. AOI21 | | Drive | X0.5